1. Field of the Invention
The present invention is related generally to semiconductor device testing and specifically to self-adaptive modification of testing procedures to optimize test completion speed without reducing test coverage.
2. Description of the Background Art
Semiconductor devices are typically fabricated in large lots on silicon wafers. The fabrication process includes various steps such as deposition, electron beam lithography, plasma etching, sputtering and other techniques well known to those skilled in the art of semiconductor fabrication. As with any manufacturing process, defects arise during semiconductor fabrication. These defects must be detected by the manufacturer before devices are delivered to customers.
There are generally three types of tests for detecting defects on semiconductor devices: DC parametric tests, AC parametric tests, and functional tests. DC parametric tests include measuring input currents, output signals, and power consumption of the semiconductor device. AC parametric tests include measuring propagation delay between input and output terminals, minimum clock pulse width, and maximum operating frequency of the semiconductor device. Functional tests include testing whether the semiconductor device functions as designed under prescribed operating conditions. Typically, a functional test is carried out by applying a test pattern to the input terminals and comparing the generated output signals with an expected pattern. Minimum or maximum power supply (Vdd) and input signals are normally used during functional tests to emulate the full range of operating conditions.
The purpose of testing integrated circuits is to guarantee with a desired degree of confidence that any device shipped to the customer will meet all of the data sheet specifications (functionality, speed, voltages, currents, reliability, etc.) over the specified set of operating conditions, and over the entire life of the device. As circuit complexity grows, full test coverage requires increasing testing costs due to the high number of tests and the time consumed to perform them. Devices including in-system programmable (ISP) circuitry, for which test signals must be input in serial fashion, have particularly high testing costs. An important engineering challenge is therefore to find a minimal set of tests that consistently passes only devices that meet predetermined quality assurance standards.
One possible approach is to drop tests that appear unnecessary, based upon a statistical test program query, due to a zero failure rate. Indeed, even a minimal set of tests performed on an entire lot of devices normally includes at least one test that is never failed. However, such tests are only consistently found in typical device lots; where process variations and flaws are present, no test result can be taken for granted. Consequently, tests cannot be dropped from a test flow without the unacceptable risk of shipping defective parts. Moreover, for different types of silicon material and integrated circuit devices, there are different subsets of "statistical never fail" tests, and it is therefore impractical to predetermine a set of such tests before testing of a given lot begins.
In the field of programmable logic devices such as Complex Programmable Logic Devices (CPLDs), to which a specific embodiment of the present invention pertains, tests are typically performed on every manufactured device to ensure proper performance of every device shipped to customers. However, as explained above, such thorough and straightforward testing requires significant time and expense. There is therefore a need in the art to provide a method and system for device testing that diminishes the time and expense presently required, without compromising quality assurance.